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DEFINITY Made Easy Tools
Issue 2, November 2000
DEFINITY Hardware
UN331C
The UN331C controls the system and executes stored programs that perform call processing activity and maintenance. The UN331C is a RISC designed around a MIPS R3000A CPU operating at 33 MHz. It employs 32-bit address and data buses to obtain and execute instructions at a rate approaching 1 instruction per clock cycle. The 256 kbyte instruction cache with burst-mode refill and 256 kbyte data cache are key to the performance of the processor. A read/write buffer chip tailors the UN331C to the call processing environment.
Peripheral devices residing on the UN331C are positioned outside the CPU cache structure and interface to the CPU through the read/write buffers. These peripherals include 512 kbytes of ROM for the monitor, counters/timers, UARTs, control/status/error registers, and the logic that provides bus arbitration and the Bus Time-Out feature.
The UN331C interfaces to the 32-bit multiplexed address/data processor bus (PM-Bus) and the 32-bit processor expansion bus (PX-Bus). The PM-Bus is for all processor write operations and single-word (4-byte) read operations. Multiple-word or burst reads are performed using the PM-Bus to transfer the address to main memory, then the words of the burst are returned using both the PM-Bus and PX-Bus.
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| Copyright� 2000 Avaya Inc |
| Send comments to MadeEasy Development Team |
| Always check at the Made Easy Web site for the most current information. |